1. Field of the Invention
The present invention generally relates to a method for forming a metal-insulator-metal (MIM) capacitor and interconnects in integrated circuits, and more particularly relates to a method for forming a metal-insulator-metal (MIM) capacitor and copper interconnects in a mixed mode signal process.
2. Description of the Prior Art
Along with the advance of semiconductor fabrication, ultra large semiconductor integration (ULSI) increasingly replaces very large semiconductor integration (VLSI) in many products and applications. Accompanying this trend, many useful fabrications of VLSI are becoming known. It is now desired to develop new fabrications.
As important example is that copper has become a promising candidate to replace aluminum of ULSI interconnections due to its better conductivity and reliability, which his more significant when the electromigration is more serious along with the decrement of the width of interconnections.
Along with the development of ULSI, layout rule will shrink and the application of the product is likely to expand the development of multi-chips of integrated functions. Hence, it is more and more important to regulate or combine copper processes and another complicated process, such that copper interconnection for MIM capacitor in a mixed mode signal process.
The object of the invention is to provide a method for forming a MIM capacitor and copper interconnections in a mixed mode signal process.
Another object of the invention is to use copper as the top and the bottom electrode so that one level of metallization can be elimintated.
In order to achieve the previous objections of the invention, a method comparing the following essential steps is provided. First, a substrate with a plurality of conductive blocks under a surface of substrate is provided. The conductive blocks can be made of a metal, such as copper. Then, a first nitride layer is deposited on the substrate and then a first inter-metal-dielectric (IMD) layer is formed thereon. Next, a second nitride layer and a second IMD layer are sequentially formed on the first IMD layer. Thereafter, a first mask is formed on the second IMD layer with a first opening to expose the second IMD layer. Next, a first etching process is performed to form a via through the second IMD layer, the second nitride layer, the first IMD layer and the first nitride layer in the first opening to expose one of those conductive blocks. Then, a second etching process is performed to form a hole to expose the first nitride layer, wherein the hole is above one of those conductive blocks. Last, a conductive material is filled into the via and the hole to form the MIM capacitor and the interconnection. The conductive material can be made of a metal, such as copper.